DAQ and Trigger
We are developing an ATCA-based general-purpose computation platform for Data AcQuisition (DAQ) and triggering for a wide range of nuclear and particle physics experiments.
Abstract:
An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field Replaceable Unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between FPGAs as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.
System Architecture:
The ATCA-based platform features high-speed P2P interconnections, by which a large and powerful DAQ and Trigger system may be constructed according to computation and communication requirements in different experiments. The system topology can be shown in the following figure:
Schematics of CNs:
On each board there are five Xilinx Virtex-4 FX60 FPGAs, four of which (No. 1 to 4) work as algorithm processors and the fifth (No. 0) as a switch interfacing to other CNs via the full-mesh backplane. Each processor FPGA has two optical links and one Gigabit Ethernets. All five FPGAs are equipped with 2 GBytes local DDR2 memory for data buffering and large look-up table purposes. On-board point-to-point I/O interconnections make it easy to partition complicated algorithm implementations, which are too large to be fitted on one single FPGA chip.
A customized Intelligent PlatformManagementController (IPMC) fulfills the ATCA requirements on power negotiation, voltage monitoring, temperature sensoring, and FPGA configuration check, etc.. It talks to the shelf manager via two I2C buses. The design is based on the AVR micro-controller and appears as an add-on card on the compute node.
PCBs:
Under the collaboration with IHEP Beijing, we have arrived at the CN PCB version 1.1. The pictures are shown below.